Looking at the ATTiny44(a) data sheet, we want to consider the CLock Prescale Register (CLKPR, 1byte):
CLKPS[3:0] gets initialized by default to 0011 (which is the value for 8 – note that this is not a binary to hex conversion) from the CKDIV8 LFuse, which by default is set to CKDIV8 (CLocK DIVision 8).
By default, the 8MHz Internal RC Oscillator is selected as clock source from the CKSEL[3:0] LFuse (see my Understanding Fuses).
The clock speed therefore is 1Mhz, i.e. if we tell the compiler in the Makefile with F_CPU = 8000000 that the chip runs at 8MHz, everything will be executed 8x slower than we expect. This is the explanation if delay_ms(double) seems ~10x slower against wall-clock time.
If we want to run at the full 8MHz and not mess with the LFuse, we simply set CLKPR to divide by 1 in code:
CLKPR = (1 << CLKPCE);
CLKPR = (0 << CLKPS3) | (0 << CLKPS2) | (0 << CLKPS1) | (0 << CLKPS0);
If we want to run at the default 1MHz, we must make sure that we don’t pass anything to the compiler that would override the #define F_CPU 1000000UL from delay.h.