/*	Code modified from http://matt16060936.blogspot.com/2012/04/attiny-pwm.html  10/27/15
		attiny45 using internal 8MHz Oscillator
		H-bridge inputs:
	 		PB0, using 0C0A for PWM  counterclockwise.
			PB1, using 0C0B for PWM  clockwise.
		Fast PWM mode used, with PWM duty cycle determined by the values of registers 0CR0A and 0CR0B.  
		See data sheet for details.



	*/


    #define F_CPU 8000000

    #include <avr/io.h>
    #include <util/delay.h>

   int main(void) {
		
		uint8_t SetValue = 0;
	
	    //
	    // set clock divider to /1
	    //
	    CLKPR = (1 << CLKPCE);
	    CLKPR = (0 << CLKPS3) | (0 << CLKPS2) | (0 << CLKPS1) | (0 << CLKPS0);
        
		/*
        Control Register A for Timer/Counter-0 (Timer/Counter-0 is configured using two registers: A and B)
        TCCR0A is 8 bits: [COM0A1:COM0A0:COM0B1:COM0B0:unused:unused:WGM01:WGM00]
        2<<COM0A0: sets bits COM0A0(0) and COM0A1(1), which (in Fast PWM mode) clears OC0A on compare-match, and sets OC0A at BOTTOM
        2<<COM0B0: sets bits COM0B0(0) and COM0B1(1), which (in Fast PWM mode) clears OC0B on compare-match, and sets OC0B at BOTTOM
        3<<WGM00: sets bits WGM00 and WGM01, which (when combined with WGM02 from TCCR0B below) enables Fast PWM mode
        */
        TCCR0A = 2<<COM0A0 | 2<<COM0B0 | 3<<WGM00;
       
        /*
        Control Register B for Timer/Counter-0 (Timer/Counter-0 is configured using two registers: A and B)
        TCCR0B is 8 bits: [FOC0A:FOC0B:unused:unused:WGM02:CS02:CS01:CS00]
        0<<WGM02: bit WGM02 remains clear, which (when combined with WGM00 and WGM01 from TCCR0A above) enables Fast PWM mode
        CS00-CS02 set prescalar, in this case /256 which makes PWM period = 256*256/8 microseconds, or 8.2 milliseconds.
        */
        TCCR0B = 0<<WGM02 | 1<<CS02| 0<<CS01| 0<<CS00;
       
        /*  initialize ADC and read PB3   */
		
		ADMUX = (0 << REFS2) | (0 << REFS1) | (0 << REFS0) // VCC ref
           | (1 << ADLAR) // left adjust (1 << ADLAR).  ADCH will contain the eight most significant bits of the conversion.
           | (0 << MUX3) | (0 << MUX2) | (1 << MUX1) | (1 << MUX0); // PB3
        ADCSRA = (1 << ADEN) // enable
           | (1 << ADPS2) | (1 << ADPS1) | (1 << ADPS0); // clock prescaler /128
		
		
		while(1)  {
		//
        // initiate conversion
        //
        ADCSRA |= (1 << ADSC);
        //
        // wait for completion
        //
        while (ADCSRA & (1 << ADSC)){
			;}
			
        
		SetValue = ADCH;				//  ADCH contains the eight most significant bits of the conversion.
		
		if (SetValue < 128){			// counter-clockwise
		SetValue= 128 - SetValue;		//
		DDRB =  0<<DDB1 | 1<<DDB0;		//Set PB0 for output, turn off PB1
		OCR0A = 2 * SetValue;			// update 0CR0A to set PWM duty cycle
		}
        else {
		SetValue = SetValue - 128;		// clockwise
		DDRB =  1<<DDB1 | 0<<DDB0;		//Set PB1 for output, turn off PB0
		OCR0B = 2 * SetValue;			//update 0CR0B to set PWM duty cycle
		}
		
		
		
        
		}
            
           
        
      
    }