Week 5
Electronics Design


This week, we have a cumulative assignment to design, print, and make an electrical circuit board. Building on previous skills, the process involves the following:

Choosing Software and Learning Eagle

Since this is my first time using PCB design software, I installed KiCad, as I understood it to be the most intuitive product. However, after discovering the Fab.lbr file in the class tutorials, I switched to Eagle since I could create a directory of components: Prior to this breakthrough, I had been struggling to match the components from the Hello Board design to those in the pre-packaged libraries, both in Eagle and KiCad. Each component seemed to have an endless number of packaging variations! But I got the hang of it as I surfed between the Hello Board design, the manufacturing descriptions for the parts, and the component libraries.

Getting the library right was a critical step to completing my design, which consisted of a schematic and board layout. And while I am averse to YouTube videos, YouTube tutorials became my best friend over this glorious Columbus Day weekend - I had so much SparkFun (pun intended) and recordings by this Jeremy Blum Eagle pro.

To create the schematic, I selected all the components from the Fab and Eagle libraries. To customize my design, I added a switch and LED. Then, I connected the components with nets and junctions, which simulate wires. I learned the fundamentals of PCB design: naming / labeling components, ascribing values to parts (e.g. resistor 10K), and adding supply sources, such as voltages and grounds. As for labeling, I realized that labeling nodes on the program header and IC1 would create electrical connections without a wire illustration. Pretty cool! Once I finished the schematic, I used it to create a board layout.

To build the board layout, I used the Ratsnest function to arrange the components within a perimeter. Then, I edited the Net Classes to determine trace width, drill, and clearance. Next, I used the AutoRouter function to optimize the traces. Initially, I made a mistake and enabled Eagle to optimize routes for the top and bottom layers of copper. However, a peer offered some pointers, and I adjusted it to optimize routes for the TOP Layer ONLY. Several times, I needed to re-arrange the components and re-instigate AutoRouter because there were airwires: Airwires flag traces that won't work on the circuit, and in my design, most were due to excessive cross-overs. But, I finally got it right, and I verified the design was 100% good-to-go with the Design Rules Check (DRC)

To wrap up the design, I exported the board layout as two images: traces and outline. I modified the layers in order to create a file that could be loaded into the PCB Mill. For the traces, I checked off "Top", and for the outline, I checked off "Dimension" in the View options. When prompted to export these files, I checked off "Monochromatic" to emulate the designs from our Electronics Production week.

Milling the Circuit Board

To print my circuit, I uploaded my traces and outline into the PCB software. Here, I learned a few more things. First, after switching between files and bits, one must click "move to origin" in order to reposition the mill. Otherwise, the mill will fail to calibrate and slice through the board. Second, for PCB designs created on a device with retina display, one must double the DPI in order to size the images correctly in the software. After I milled the traces, I forgot to re-adjust the DPI when I loaded the image for my outline. So, the mill cut a 3-inch perimeter around my traces instead. Luckily, no traces were affected, and I salvaged my board by slicing off two edges to complete the outline.

Re-calibrating and Soldering Components

The circuit board looked pretty good, but after cross-referencing it with the design in Eagle, I realized that some of the traces had fused together, which implies that there could be a short circuit that breaks it. Therefore, I couldn't solder the components, as I need to make some adjustments. For example, I will experiment with the net class width and component layout so that traces are spread further apart.