;
; DPA trunk
;
;.include "tn44def.inc"
.device ATtiny44
;
; pin definitions
;

; (master in) slave out
.equ audio_so = PA7 ;
.equ audio_so_port = PORTA ;
.equ audio_so_pin = PINA ; 
.equ audio_so_ddr = DDRA ;
; (master out) slave in
.equ audio_si = PB2 ;
.equ audio_si_port = PORTB ;
.equ audio_si_pin = PINB ;
.equ audio_si_ddr = DDRB ;

.equ radio_so = PA1 ;
.equ radio_so_port = PORTA ;
.equ radio_so_pin = PINA ; 
.equ radio_so_ddr = DDRA ;
.equ radio_si = PB2 ;
.equ radio_si_port = PORTA ;
.equ radio_si_pin = PINA ;
.equ radio_si_ddr = DDRA ;

.equ serial_si = PA0 ;
.equ serial_si_port = PORTA ;
.equ serial_si_ddr = DDRA ;
.equ serial_si_pin = PINA ;

;
; register definitions
;
.def bit_count = R16; bit counter
.def temp = R17; temporary storage
.def temp1 = R18; temporary storage
.def txbyte = R19; transmit byte
.def rxbyte = R20; receive byte

.equ sb = 1 ; number of stop bits
;
; putchar
; assumes no line driver (doesn't invert bits)
;
.macro putchar
   ldi bit_count, 9+sb; 1 + 8 + sb
   com txbyte; invert everything
   sec ; set start bit
   putchar0:
      brcc putchar1 ; if carry set
      sbi @0, @1; send a '0'
      rjmp putchar2; else
   putchar1:
      cbi @0, @1 ; send a '1'
      nop ; even out timing
   putchar2:
      rcall bit_delay ; one bit delay
      rcall bit_delay
      lsr txbyte ; get next bit
      dec bit_count ; if not all bits sent
      brne putchar0 ; set next bit
   ret;
.endmacro
;
; getchar
; assumes no line driver (doesn't invert bits)
;
.macro getchar
   ldi bit_count, 8+sb ; 8 data bit + 1 stop bit
   getchar1:
      sbis @0, @1 ; wait for start bit
      rjmp getchar1
      rcall bit_delay ; 0.5 bit delay
   getchar2:
      rcall bit_delay ; 1 bit delay
      rcall bit_delay ;
      clc ; clear carry
      sbis @0, @1 ; if RX pin high skip
         sec ; otherwise set carry
      dec bit_count
      breq getchar3 ; return if all bits read
      ror rxbyte ; otherwise shift bit into receive byte
      rjmp getchar2 ; go get next bit
   getchar3:
      ret
.endmacro
   
   

;
; code segment
;
.cseg
.org 0
rjmp reset
;
; bit delay
; serial bit delay
;
;.equ b = 13 ; 9600 baud (clock /8)
;.equ b = 130 ; 9600 baud (clock /1)
.equ b = 8 ; 115200 baud (clock /1)
;.equ b = 6 ; crazy speed
;.equ b = 4 ; ludicrous speed
bit_delay:
   ldi temp, b
   bitloop:
      dec temp
      brne bitloop
   ret

putchar_audio:
   putchar audio_si_port, audio_si
putchar_radio:
   putchar radio_si_port, radio_si
putchar_serial:
   putchar serial_si_port, serial_si

getchar_audio:
   getchar audio_so_pin, audio_so
getchar_radio:
   getchar radio_so_pin, radio_so

reset:
   ;
   ; set stack pointer to top of RAM
   ;
   ldi temp, high(RAMEND)
   out SPH, temp
   ldi temp, low(RAMEND)
   out SPL, temp
   ;
   ; set clock divider to /1
   ;
   ldi temp, (1 << CLKPCE)
   ldi temp1, (0 << CLKPS3) | (0 << CLKPS2) | (0 << CLKPS1) | (0 << CLKPS0)
   out CLKPR, temp
   out CLKPR, temp1
   ;
   ; init transmit/receive pins
   ;
   sbi audio_si_port, audio_si
   sbi audio_si_ddr, audio_si
   cbi audio_so_ddr, audio_so
   
   sbi radio_si_port, radio_si
   sbi radio_si_ddr, radio_si
   cbi radio_so_ddr, radio_so

   sbi serial_si_port, serial_si
   sbi serial_si_ddr, serial_si
   ;
   ; main loop
   ;
   ldi rxbyte, 0
   main_loop:
      rcall getchar_audio
      mov txbyte, rxbyte
      rcall putchar_serial
      rjmp main_loop