;
; IR CODE 
; Serial driver EXTRACTED FROM:
; -----hello3.step.asm
; -----step response measurement for hello3
; -----Neil Gershenfeld CBA MIT 8/22/04
; rest by ED BAAFI
; definitions
;
.include "tn13def.inc"

.equ wait = 0x00 ; wait state 
.equ init = 0xaa ; init state 
.equ init2= 0x0a ; init2 state
.equ read = 0xff ; read state
.equ skip = 0x0f ; skip state
.equ zero = 0 ;
.equ one = 0 ;
.equ txpin = PB1 ; serial transmit pin
.equ irpin = PB2 ; ir module pin

.def S =R0 ; Sreg storage
.def inttemptime =R1 ;temp storage for time in int serv routine
.def inttemp1 = R2
.def S1 =R3 Sreg storage for main
.def bitcnt = R16 ; bit counter
.def timeSincePC = R17 ;
.def system = R18; system code
.def command = R19; command code
.def txbyte = R20 ; data byte

.def irbits = R21 ; upwards high byte
.def temp = R23
.def temp2 = R24 ;  byte built to send 2 pc
.def state = R25  ;state of device - read/wait/init
.def trequart = R26 ;threequarters of bit time measured during start bit
.def inttemp2 = R27
.def outputready = R28
;
; start of code
;
.cseg
.org 0
 rjmp reset ; jump to reset routine
.org PCINT0addr
 rjmp PCIntV2 ; PCINT2 vector (pin PB2)
.org TIM0_OVF0addr
 rjmp TimOvf0V ; Timer/Counter 0 overflow vector


;
; putchar
; assumes no line driver (doesn't invert bits)
;
.equ sb = 1; number of stop bits
putchar:

in S1, SREG ;store status reg
cli
   ldi bitcnt, 9+sb; 1+8+sb
   com txbyte; invert everything
   sec; set start bit
   putchar0:
      brcc putchar1; if carry set
      sbi PORTB, txpin; send a '0'
      rjmp putchar2; else
   putchar1:
       cbi PORTB, txpin ; send a '1'
       nop ; even out timing
   putchar2:
       rcall bitdelay; one bit delay
       rcall bitdelay
       lsr txbyte; get next bit
       dec bitcnt; if not all bits sent
       brne putchar0; send next bit
out sreg,S1 ;restore SREG
sei
   ret;
;
; bit delay
;
.equ b = 78 ; OSCCAL = 0xff 9600 bps
bitdelay:
   ldi temp, b
   bitloop:
      dec temp
      brne bitloop
   ret



;
; main program
;
reset:

   ldi temp, (1<<CLKPCE)
   ldi temp2, ((0 << CLKPS3) | (0 << CLKPS2) | (0 << CLKPS1) | (1 << CLKPS0))
   out CLKPR, temp ; write CLKPCE to change clock prescaler
   out CLKPR, temp2 ; set clock to 9.6MHz/2


   ;
   ; set up PCINT2
   ;
   ldi temp,(1<<PCIE); pin change int mask set
   out GIMSK, temp
   ldi temp,(1<<PCINT2); pinchange2 int mask set
   out PCMSK, temp

   ;ldi outputready, 0
   ; set up OVF1 - ticks2wait = quantum*ck/1000*prescaler
   ;


   ldi temp, 0x00 ; Set as Normal -overflow counter
   out TCCR0A, temp

   ldi temp, 0x01 ; clock prescaler = clk/1
   out TCCR0B, temp

   ldi temp, 1<<TOIE0 ;enable Timer0 overflow int
   out TIMSK0, temp


   ;
   ; set output pins
   ;
   sbi PORTB, txpin ; set initial value
   sbi DDRB, txpin ; set for output

   sei ; enable ints

   ;initialize state to wait and bitcount
   ldi state, wait

   ldi irbits, 12


   ldi timeSincePC,0
   ldi system, 0
   ldi command, 0
ldi outputready, 0

   loop:

 cpi outputready, 1
 breq output

 rjmp loop ; Infinite loop

 output:
  mov txbyte, command
  rcall putchar
  mov txbyte, system
  rcall putchar
  ldi outputready, 0
ldi command, 0 ;test
ldi system, 0 ;might be better place
  rjmp loop ; Infinite loop


;timer0 overflow vector
TimOvf0V:

 in S,sreg  ;store SREG
 cpi timeSincePC,255 ;go to waitstate after 53usx256=13.5ms
 breq waitstate

 inc timeSincePC ;update every 53us?


 rjmp TimOvf0_exit

 waitstate:
  ldi timeSincePC, 0
  ldi state, wait
  ldi command, 0
  ldi system, 0
  ldi irbits, 12

 TimOvf0_exit:
  out sreg,S ;restore SREG
  reti
clr timeSincePC;start counting to avoid going back to wait


;pin change (pb2) interrupt vector
PCIntV2:
in S,sreg  ;store SREG

 mov  inttemptime, timeSincePC ;store time since pin change
 clr timeSincePC ;restart counting time since pin change

 cpi state, wait ; if pin change in wait state
 breq waitPC; then go to waitPC

 cpi state, init  ; if pin change in init state
 breq initPC  ; then go to initPC

 cpi state, init2  ; if pin change in init2 state
 breq initPC2  ; then go to initPC2
 
  cpi state, skip  ; if pin change in skip state
  breq skipPC  ; then go to skipPC

    ;else must be in read state

 readPC:
  
  dec irbits ;decrement bitcount
  ldi state, skip ;go to skip state  

  ;if time since last pc is within 1 bitsize range
   cp inttemptime, trequart
   brge readone ;then go to readone

   ;else read zero
   readzero:
     clc ; store 0 in carry
     rol command
     rol system
     rjmp PCInt_exit

    readone:
      sec ; store 1 in carry
      rol command
      rol system
      rjmp PCInt_exit
 

 skipPC:
   ldi state, read; go to read state
   rjmp PCInt_exit
 
 
  
 waitPC:
  ldi state, init ;go to init state
  rjmp PCInt_exit;do nothing now -error detect  later


 initPC:; error detect later 
  
  ldi state, init2 ; go to init2 state
  rjmp PCInt_exit

  initPC2:
  
  mov inttemp1, inttemptime ; it1= itt = 1/2 bittime
  lsr inttemp1 ; it1 = 1/4 bittime
  add inttemptime, inttemp1; itt += it1 = 3/4 bit time
  mov trequart, inttemptime ; store 3/4 bit time

  ldi state, read ;go to read state
  rjmp PCInt_exit

 PCInt_exit:


  cpi irbits,0 ;if last bit
  breq lastbit ;goto lastbit
  out SREG, S
  reti

  lastbit:

   ldi irbits, 12
   ldi outputready, 1

   out SREG, S
   reti