gavrasm Gerd's AVR assembler version 2.1 (C)2006 by DG4FAC
----------------------------------------------------------
Source file: hello.step.45.asm
Hex file:    hello.step.45.hex
Eeprom file: hello.step.45.eep
Compiled:    27.10.2007, 14:26:04
Pass:        2
     1: ;
     2: ; hello.step.45.asm
     3: ;
     4: ; read and send step response
     5: ;
     6: ; Neil Gershenfeld
     7: ; CBA MIT 10/27/07
     8: ;
     9: ; (c) Massachusetts Institute of Technology 2007
    10: ; Permission granted for experimental and personal use;
    11: ; license for commercial sale available from MIT.
    12: 
    13: .include "tn45def.inc"
 -> Warning 009: Include defs not necessary, using internal values!
   File: hello.step.45.asm, Line: 13
   Source line: .include "tn45def.inc"
    14: ;
    15: ; definitions
    16: ;
    17: .equ tx_pin = PB2 ; transmit pin
    18: .equ charge_pin = PB4 ; charging pin
    19: ;
    20: ; registers
    21: ;
    22: .def bit_count = R16 ; bit counter
    23: .def temp = R17 ; temporary storage
    24: .def temp1 = R18 ; temporary storage
    25: .def txbyte = R19 ; data byte
    26: .def delay_count = R20 ; delay counter
    27: .def uplo = R21 ; up low byte
    28: .def uphi = R22 ; up hi byte
    29: ;
    30: ; code segment
    31: ;
    32: .cseg
    33: .org 0
    34: 000000   C01D  rjmp reset ; jump to reset routine
    35: ;
    36: ; bit delay
    37: ; serial bit delay
    38: ;
    39: ;.equ b = 13 ; 9600 baud (clock /8)
    40: .equ b = 130 ; 9600 baud (clock /1)
    41: ;.equ b = 8 ; 115200 baud (clock /1)
    42: bit_delay:
    43: 000001   E812  ldi temp, b
    44:    bitloop:
    45: 000002   951A  dec temp
    46: 000003   F7F1  brne bitloop
    47: 000004   9508  ret
    48: ;
    49: ; putchar
    50: ; assumes no line driver (doesn't invert bits)
    51: ;
    52: .equ sb = 1; number of stop bits
    53: putchar:
    54: 000005   E00A  ldi bit_count, 9+sb; 1+8+sb
    55: 000006   9530  com txbyte; invert everything
    56: 000007   9408  sec; set start bit
    57:    putchar0:
    58: 000008   F410  brcc putchar1; if carry set
    59: 000009   9AC2  sbi PORTB, tx_pin; send a '0'
    60: 00000A   C002  rjmp putchar2; else	
    61:    putchar1:
    62: 00000B   98C2  cbi PORTB, tx_pin	; send a '1'
    63: 00000C   0000  nop ; even out timing
    64:    putchar2:
    65: 00000D   DFF3  rcall bit_delay; one bit delay
    66: 00000E   DFF2  rcall bit_delay
    67: 00000F   9536  lsr txbyte; get next bit
    68: 000010   950A  dec bit_count; if not all bits sent
    69: 000011   F7B1  brne putchar0; send next bit
    70: 000012   9508  ret;
    71: ;
    72: ; char_delay
    73: ; delay between characters
    74: ;
    75: char_delay:
    76: 000013   EF1F  ldi temp, 255
    77: char_delay_loop:
    78: 000014   E02A  ldi temp1, 10
    79:    char_delay_loop1:
    80: 000015   952A  dec temp1
    81: 000016   F7F1  brne char_delay_loop1
    82: 000017   951A  dec temp
    83: 000018   F7D9  brne char_delay_loop
    84: 000019   9508  ret
    85: ;
    86: ; settle
    87: ; delay for charge to settle
    88: ;
    89: .equ delay = 255
    90: settle:
    91: 00001A   EF1F  ldi temp, delay
    92:    settleloop:
    93: 00001B   951A  dec temp
    94: 00001C   F7F1  brne settleloop
    95: 00001D   9508  ret
    96: ;
    97: ; main program
    98: ;
    99: reset:
   100:    ;
   101:    ; set clock divider to /1
   102:    ;
   103: 00001E   E810  ldi temp, (1 << CLKPCE)
   104: 00001F   E020  ldi temp1, (0 << CLKPS3) | (0 << CLKPS2) | (0 << CLKPS1) | (0 << CLKPS0)
   105: 000020   BD16  out CLKPR, temp
   106: 000021   BD26  out CLKPR, temp1
   107:    ;
   108:    ; set stack pointer to top of RAM
   109:    ;
   110: 000022   E011  ldi temp, high(RAMEND)
   111: 000023   BF1E  out SPH, temp
   112: 000024   E51F  ldi temp, low(RAMEND)
   113: 000025   BF1D  out SPL, temp
   114:    ;
   115:    ; init comm and charge pins for output
   116:    ;
   117: 000026   9AC2  sbi PORTB, tx_pin
   118: 000027   9ABA  sbi DDRB, tx_pin
   119: 000028   9AC4  sbi PORTB, charge_pin
   120: 000029   9ABC  sbi DDRB, charge_pin
   121:    ;
   122:    ; init A/D
   123:    ;
   124: 00002A   983C  cbi ADMUX, REFS2 ; use Vcc as reference
   125: 00002B   983F  cbi ADMUX, REFS1 ; "
   126: 00002C   983E  cbi ADMUX, REFS0 ; "
   127: 00002D   983D  cbi ADMUX, ADLAR ; right-adjust result
   128: 00002E   983B  cbi ADMUX, MUX3 ; set MUX to ADC3
   129: 00002F   983A  cbi ADMUX, MUX2 ; "
   130: 000030   9A39  sbi ADMUX, MUX1 ; "
   131: 000031   9A38  sbi ADMUX, MUX0 ; "
   132: 000032   9A37  sbi ADCSRA, ADEN ; enable A/D
   133: 000033   9832  cbi ADCSRA, ADPS2 ; set prescaler to /2
   134: 000034   9831  cbi ADCSRA, ADPS1 ; "
   135: 000035   9830  cbi ADCSRA, ADPS0 ; "
   136:    ;
   137:    ; start main loop
   138:    ;
   139:    loop:
   140:       ;
   141:       ; loop over delays
   142:       ;
   143: 000036   EF4E  ldi delay_count, 254
   144:       delayloop:
   145:          ;
   146: 	 ; settle sample and start upward step response
   147: 	 ;
   148: 000037   98C4  cbi PORTB, charge_pin
   149: 000038   DFE1  rcall settle
   150: 000039   2F14  mov temp, delay_count
   151: 00003A   9AC4  sbi PORTB, charge_pin
   152: 	 ;
   153:          ; wait for delay
   154: 	 ;
   155: 	 addelayup:
   156: 00003B   951A  dec temp
   157: 00003C   F7F1  brne addelayup
   158:          ;
   159: 	 ; read response
   160: 	 ;
   161: 00003D   9A36  sbi ADCSRA, ADSC ; start conversion
   162:          adloopup:
   163: 00003E   9936  sbic ADCSRA, ADSC ; loop until complete
   164: 00003F   CFFE  rjmp adloopup
   165: 	 ;
   166: 	 ; save conversion
   167: 	 ;
   168: 000040   B154  in uplo, ADCL ; get low byte
   169: 000041   B165  in uphi, ADCH ; get high byte
   170:          ;
   171: 	 ; settle sample and start downward step response
   172: 	 ;
   173: 000042   DFD7  rcall settle
   174: 000043   2F14  mov temp, delay_count
   175: 000044   98C4  cbi PORTB, charge_pin
   176: 	 ;
   177:          ; wait for delay
   178: 	 ;
   179: 	 addelaydown:
   180: 000045   951A  dec temp
   181: 000046   F7F1  brne addelaydown
   182:          ;
   183: 	 ; read response
   184: 	 ;
   185: 000047   9A36  sbi ADCSRA, ADSC ; start conversion
   186:          adloopdown:
   187: 000048   9936  sbic ADCSRA, ADSC ; loop until complete
   188: 000049   CFFE  rjmp adloopdown
   189: 	 ;
   190: 	 ; send conversions
   191: 	 ;
   192: 00004A   B134  in txbyte, ADCL ; low down byte
   193: 00004B   DFB9  rcall putchar
   194: 00004C   B135  in txbyte, ADCH ; hi down byte
   195: 00004D   DFB7  rcall putchar
   196: 00004E   2F35  mov txbyte, uplo ; low up byte
   197: 00004F   DFB5  rcall putchar
   198: 000050   2F36  mov txbyte, uphi ; hi up byte
   199: 000051   DFB3  rcall putchar
   200: 000052   DFC0  rcall char_delay
   201: 000053   954A  dec delay_count
   202: 000054   954A  dec delay_count
   203: 000055   F709  brne delayloop
   204:       ;
   205:       ; send 1 2 3 4 for framing
   206:       ;
   207: 000056   E031  ldi txbyte, 1
   208: 000057   DFAD  rcall putchar
   209: 000058   E032  ldi txbyte, 2
   210: 000059   DFAB  rcall putchar
   211: 00005A   E033  ldi txbyte, 3
   212: 00005B   DFA9  rcall putchar
   213: 00005C   E034  ldi txbyte, 4
   214: 00005D   DFA7  rcall putchar
   215: 00005E   DFB4  rcall char_delay
   216: 00005F   CFD6  rjmp loop

Program             :       96 words.
Constants           :        0 words.
Total program memory:       96 words.
Eeprom space        :        0 bytes.
Data segment        :        0 bytes.
Compilation completed, no errors.
Compilation endet 27.10.2007, 14:26:04
