Links with examples on AVR programming:
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C-program: http://academy.cba.mit.edu/classes/embedded_programming/hello.ftdi.44.echo.c
Make-file: http://academy.cba.mit.edu/classes/embedded_programming/hello.ftdi.44.echo.c.make
Programming work-flow using make-file: http://academy.cba.mit.edu/classes/embedded_programming/hello.ftdi.44.program.png

Note that you must power the board, e.g., through an FTDI cable in order to program it with an ISP.


Relevant things gleaned from ATtiny44 data sheet:
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PortB has 4 bi-directional bits. Two are being used for XTAL and one for RESET so that leaves only one here which is PB2.

PortA has 8 bi-directional bits.

PortA can also be used as analog inputs to the ADC.

8-bit timer counter has two PWM channels.

16-bit timer counter has two PWM channels.

8-channel, 10-bit ADC.

Programmable gain stage (1x or 20x) for 12 differential ADC channel PAIRS: cool, this is built-in differential amplifiers!

Interrupts: when an interrupt occurs, the global interrupt enable I-bit is cleared, disabling all interrupts. The user can then manually set the I-bit from within an interrupt in order to allow nested interrupts.

Overview of bitwise operation:

X |= A<<B

translates to "or X with (A shifted to the left by B bits)"

Clocks:

internal 8 MHz oscillator

external clock

XTAL

CLKPR register: Need to set clock prescale change enable bit to 1 (bit 7), and assign 4 clock pre-scale select bits (bits 0 to 3)

"To avoid unintentional changes of clock frequency, a special write procedure must be followed
to change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in
CLKPR to zero.
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted."

Digital pins:

"All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.
This means that the direction of one port pin can be changed without unintentionally changing
the direction of any other pin with the SBI and CBI instructions."

Analog to digital conversion:

A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.

Auto Triggering is
enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is
selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (see description of the ADTS
bits for a list of the trigger sources).

By default, the successive approximation circuitry requires an input clock frequency between 50
kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the
input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate. It is
not recommended to use a higher input clock frequency than 1 MHz.

The ADC module contains a prescaler, as illustrated in Figure 16-3 on page 135, which generates
an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The
prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment
the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as
long as the ADEN bit is set, and is continuously reset when ADEN is low.