//
// Neil Gershenfeld
// 11/18/12
// Modified by Grace Copplestone
// 11/29/16
// (c) Massachusetts Institute of Technology 2012
// This work may be reproduced, modified, distributed,
// performed, and displayed for any purpose. Copyright is
// retained and must be preserved. The work is provided
// as is; no warranty is provided, and users accept all 
// liability.
//

#include <avr/io.h>
#include <util/delay.h>

#define output(directions,pin) (directions |= pin) // set port direction for output
#define set(port,pin) (port |= pin) // set port pin
#define clear(port,pin) (port &= (~pin)) // clear port pin
#define pin_test(pins,pin) (pins & pin) // test for port pin
#define bit_test(byte,bit) (byte & (1 << bit)) // test for bit set

#define on_delay() _delay_us(30) // PWM on time
#define medium_off_delay() _delay_us(10) // PWM medium off time
#define PWM_count 20000 // number of PWM cycles

#define bridge_port_IN1 PORTA // H-bridge port
#define bridge_port_IN2 PORTA // H-bridge port
#define bridge_port_IN1B PORTB // H-bridge port
#define bridge_port_IN2B PORTA // H-bridge port


#define bridge_direction DDRA // H-bridge direction

#define IN1 (1 << PA3) // IN1
#define IN2 (1 << PA2) // IN2
#define IN1B (1 << PB2) // IN1
#define IN2B (1 << PA7) // IN2


int main(void) {
   //
   // main
   //
   static uint16_t count;
   static uint8_t cycle;
   //
   // set clock divider to /1
   //
   CLKPR = (1 << CLKPCE);
   CLKPR = (0 << CLKPS3) | (0 << CLKPS2) | (0 << CLKPS1) | (0 << CLKPS0);
   //
   // initialize H-bridge pins
   //
   clear(bridge_port_IN1, IN1);
   output(bridge_direction, IN1);
   clear(bridge_port_IN2, IN2);
   output(bridge_direction, IN2);
   clear(bridge_port_IN1B, IN1B);
   output(bridge_direction, IN1B);
   clear(bridge_port_IN2B, IN2B);
   output(bridge_direction, IN2B);

   //
   // main loop
   //
   while (1) {
         
         
         clear(bridge_port_IN1, IN1);
         clear(bridge_port_IN1B, IN1B);         

         for (count = 0; count < PWM_count; ++count) {
            set(bridge_port_IN2, IN2);
            set(bridge_port_IN2B, IN2B);

            on_delay();

            clear(bridge_port_IN2, IN2);
            clear(bridge_port_IN2B, IN2B);

            medium_off_delay();

            }
         }
      }