“There is no reason anyone would want a computer in their home.”

– Ken Olsen, founder of DEC, 1977

Today there are two big names in the PC microprocessor market: Intel and AMD. AMD was on the verge of bankruptcy just four years ago, but now their CPUs are beating Intel’s in many benchmarks, and they’re rapidly gaining market share. This has been a wake up call for Intel, and forced them to step up their formerly stagnating innovation game lest AMD eat their lunch.

By sales volume in this vertical, Apple is also a big name, but it’s not possible to integrate their technology outside of their walled garden.

CISC (e.g. x86)

Even as we speak, systems programmers are doing pointer arithmetic so that children and artists can pretend that their x86 chips do not expose an architecture designed by Sauron.

– James Mickens, Professor of Computer Science at Harvard

Intel and AMD both build x86 processors. This ISA traces its origins back to the legendary Intel 8086, which was used in the first IBM PC. Since then it’s been extended to 64 bits (known as the amd64 instruction set, as Intel was busy betting on Itanium).

It is unabashedly a complex instruction set computer (CISC) architecture, in that it has a bewildering array of instructions (the Intel x86_64 ISA reference manual is several thousand pages long, in multiple volumes). Characteristically, CISC instructions:

  • Are variable-length
  • Are often very application-specific
  • Execute in highly-variable amounts of time

Instruction decode pipeline

CISC instructions are fetched from memory, decoded, and issued by a sequence of functional units known as the instruction decode pipeline. The main point at a high level is that this process is complicated and consumes a significant amount of resources.

Decode produces microcode, which is what actually coordinates the ALUs, FPUs, and other functional units in the processor — the machine code instructions that are in your binary are only seen by the decode pipeline. It reinterprets these into a (much longer) sequence of microcode instructions, the architecture of which looks a lot like RISC. Instructions are fixed-length, simple, more numerous (in terms of count after interpretation), and they execute in known cycle counts.

The point is that morally, Intel processors (internally) run on an essentially-RISC architecture because this is the only sane way to implement the silicon, but they present a CISC ISA externally for compatiblity and extensibility.

RISC (e.g. Arm, RISC-V)

Reduced instruction set computer (RISC) architectures offer a comparatively-small number of simpler instructions with unambiguous (context-free) decode semantics and predictable execution times.

RISC binaries typically contain many more instructions than CISC ones as a result, but as mentioned, do not have an involved decoding process and are much closer to 1-1 with the microcode (if a microcode-machine-code separation is even required).

RISC architectures tend to be more power efficient than CISC architectures, so unsurprisingly RISC reigns supreme in the mobile market. Most phones use one of the ARM architectures. ARM/RISC is also making headway into the server market. Amazon’s recently developed Graviton processors are ARM. ARM cores are even appearing in the PC market: the M3 chip powering Apple’s newest laptops is also a custom ARM chip. The M series has a novel architecture that incorporates high efficiency CPU cores, high speed CPU cores, a GPU, and dedicated neural net hardware on a single die, all sharing the same memory space.

Notionally, you can get a high-core-count aarch64 (64-bit Arm) machine on Oracle’s free tier (but I’ve never gotten the signup to work).

Arm

Arm (the company) designs and licenses the Arm instruction set architecture (ISA), which runs most smartphones, Apple Silicon, and most embedded devices in the world. They do not actually produce physical silicon, but make money off of the license royalties. If you buy an MCU running Arm code, some of the purchase price went to Arm.

It is worth mentioning that there are several versions of the Arm ISA (e.g. armv{6,7,8,...}-eabi{,hf}) that different devices use — you compile for one of them depending on your platform. The hf means “hard-float” and indicates that there is a dedicated floating point unit in hardware — its absence means that floats are calculated in software and will be especially slow/inefficient.

It is worth mentioning that Thumb exists, which is a rephrasing of the standard 32-bit Arm instruction set into mixed 16-bit (most commonly-used) and 32-bit instructions (less commonly used). Using Thumb can significantly reduce code size and can be enabled on a code-section-by-code-section basis.

RISC-V

RISC-V is a new open RISC ISA envisaged essentially as a replacement to Arm without the licensing fees. Many companies in industry are members of the consortium, including Google, Nvidia, and Intel.

Relatively recently, many low-cost chips have come to market on the RISC-V architecture, including Wch’s famous 10-cent RISC-V MCU, the CH32V003 (2KiB RAM, 16KiB flash).

Notably, the ESP32 C-series are also RISC-V, rather than Espressif’s native Xtensa architecture (which, after a long time of ESP chips existing, almost no tooling natively supports, and you still need to get the custom Espressif forks).