Week 8

Problem Set 8

April 7th

all problems from Chapter 10: Semiconductor Devices

Problem 4

Cadence Spectre (SPICE) simulations of tristate inverter

first design:

• all nmos are 240nm channel width
• all pmos are 480nm channel width this works, but the floating (high impedence) output is too close to high voltage

So I’m going to try to iterate with the internal inverter on the control line having different channel widths to bring the high impedence values down a bit

. . . it seemed to make no difference

but decreasing the input control voltage does - although this doesn’t seem like the best design practice